As VLSI technology progresses, the characteristic feature size of VLSI devices continually decreases from one technology generation to the next. Smaller feature-size devices enable a designer to fit higher-complexity systems on chip (SoC) onto a smaller die area, to increase the operating frequency, as well as to reduce the operating voltages, power consumption and heat dissipation of the device. These advances in VLSI technology create a need for reusing circuit designs, proven and verified in one technology, in another technology. In some cases, migration of circuits from one technology to another is performed manually. Manual migration, however, is often a labor-intensive, tedious, slow and expensive process.
Several methods and systems are known in the art for automatic migration of digital circuitry from one technology to another. Typically, these methods use “optical scaling,” in which the dimensions of components of the source circuit are geometrically scaled to fit the target technology feature size. Such automatic conversion methods are described, for example, by Dennard et al. in “Design of Ion-Implanted MOSFETs with Very Small Physical Dimensions,” IEEE Journal of Solid-State Circuits, volume SC-9, October 1974, pages 256-268.
Optical scaling methods are often unsuitable for converting analog and mixed-signal (A&MS) circuits, such as clock generation circuitry, input/output (I/O) circuits, analog-to-digital and digital-to-analog converters (ADC, DAC). Several methods are known in the art for converting A&MS designs. For example, Galup-Montoro, et al., describe a conversion procedure that follows a set of resizing rules in “Resizing Rules for MOS Analog-Design Reuse,” IEEE Design and Test of Computers (19:2), March/April 2002, pages 50-58.
Hammouda et al. describe a method for automatic circuit resizing between different technologies in “A Fully Automated Approach for Analog Circuit Reuse,” Proceedings of the Fourth IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Canada, July 2004. The method studies the original design, extracts its major features (basic device and block features, device matching, parasitics and symmetry) and reproduces a resized design in the target technology having the same performance as the original design. A similar method is described by the same authors in “Analog IP Migration Using Design Knowledge Extraction,” Proceedings of the 26th IEEE Custom Integrated Circuits Conference, San Jose, Calif., September 2004, pages 333-336.
Some migration methods perform multivariate parameter optimization. For example, Funaba et al. describe an approach for technology scaling of metal-oxide semiconductor (MOS) analog circuits in “A Fast and Accurate Method of Redesigning Analog Subcircuits for Technology Scaling,” Analog Integrated Circuits and Signal Processing (25:3), December 2000, pages 299-307. The authors describe a circuit optimization method based on matching equivalent circuit parameters between a previously designed circuit and the circuit undergoing redesign. Optimization methods are also used in a circuit sizing and optimization tool called Virtuoso® NeoCircuit, produced by Cadence Design Systems, Inc. (San Jose, Calif.). Additional details regarding this product can be found at www.cadence.com/products/custom_ic/neocircuit/index.aspx.